Power control device and method for calibrating the power of a transmitter or receiver in a mobile communication network

ABSTRACT

The invention relates to a power control device and method for calibrating the power of a transmitter or receiver in a mobile communication network comprising an antenna array, wherein burst signals are transmitted to, or received by, the antenna array. The calibration of the transmission or receiving power of the transmitter or receiver includes a summing step for summing transmission or reception signals of the antenna array, and a common calibrating step for commonly calibrating the summed signals.

FIELD AND BACKGROUND OF THE INVENTION

The invention relates to a power control device and method forcalibrating the power of a transmitter or receiver of a mobilecommunication network in which burst signals are applied to thetransmitter. The burst signals include a fixed training sequence.

More generally, the invention relates to Power Control, in particularDigital Power Control of a transmitter such as a Transceiver (TRX, e.g.Transceiver Card) or a BTS (Base Transceiver Station) Transmitter. Morespecifically, the invention aims at providing a power control functionapplicable to a device, system, and method requiring power calibration.

In existing GSM compatible basestations, Power Control is implemented bya combination of two methods: closed loop, when the transmitter is on,and open loop when the transmitter is off. The closed loop mode is areal time control in which the output power is sampled and compared to areference signal, and the gain is corrected. The closed loop part of thepower control operation is also used to control the ramp shape betweentimeslots so that the power versus time mask is met.

The open loop part of the power control function is used in the offperiod between timeslots as the linear range of the output detectorlimits the closed loop operation.

In the standard GSM system, with a constant RF (Radio Frequency)envelope, power control can be easily carried out utilizing anintegrator as a loop filter. If there is any ripple on the envelope, theintegrator, depending upon the loop bandwidth, attempts to recover thevariation on the envelope by altering the attenuation on the RF path.However, the analog (closed loop) power control schemes as used withGMSK (Gaussian Minimum Shift Keying), have difficulty with EDGE(Enhanced Data for GSM Evolution) 8PSK modulation, as the signal has nolonger a constant envelope.

The analog power control has been enhanced for EDGE by adding a replicaof the modulation envelope onto the power control voltage and comparingit to the detected voltage. Switching the loop bandwidth during theburst enables this scheme to meet the ramping requirements of GSM, makethe power control scheme less sensitive to delay and minimise amplitudeerror.

As mentioned above, the analog scheme requires a combination of closedloop and open loop control as the linear range of the detector is notsufficient for the Tx Off state (Tx=transmitter). Such as solution isdifficult to implement and often causes distortion of the signal due toswitching transients caused by the switching of the loop bandwidth.Transients may also occur when switching between closed loop and openloop operation as the detector range is not sufficient to detect thewhole envelope. Additionally, as the power ramping is controlled by theclosed loop, overshoot of the ramp often occurs, giving type approvaldifficulties.

Further, when building a smart antenna (SA) BTS utilising beam steeringthe relative losses and phase lengths between the N columns of the arrayare critical to performance. These relative differences are not constantover time, temperature and frequency. The phase length and losses needto be measured in a non-obtrusive fashion to meet type approvalrequirements. The measurement and adjustment of these differences needsto be automatic.

In the past, beam steering systems have tended to use individual RFline-ups for each transmit path, with the calibration being performed inthe baseband processing, which has resulted in very expensive systems.

SUMMARY OF THE INVENTION

The invention provides a device and/or method with enhanced possibilityof effective and yet simple power calibration.

The present invention provides a device and/or method as defined in theindependent claims or any of the dependent claims.

The phase lengths and losses between the N columns of a smart antenna(SA) BTS utilising beam steering can be measured in a non-obtrusivefashion. The measurement and adjustment of these differences isperformed automatically so as to provide good performance.

The invention provides a simple and effective calibration system andmethod.

In accordance with the invention, a single RF lineup can exist frombaseband up to final RF, where the signal is split and fed to thephasing/gain control network.

The measurement of calibration preferably has two parts, TX and Rx. Bothuse a simple passive coupling network in the antenna array and acalibration board which works at mobile frequencies (e.g. the RF from amobile).

To calibrate the transmit side the BTS may preferably transmit GSM dummybursts to the calibration board. To calibrate the Receive side thecalibration board may transmit dummy bursts to the BTS. With some DSPprocessing the relative gain and phase values can then be calculated.The means, e.g. chipset, of a mobile terminal can be used for thecalibration.

In accordance with a preferred implementation of the invention, thetraining sequence (also known as midamble) is used to measure power.

Digital ramping may be used with the baseband functions. The powercontrol is working open loop at all times. Therefore, the problemsrelated to EDGE envelope variations are removed.

The digital Power Calibration and control loop according to a preferredimplementation of the invention as described above and below removes theabove mentioned problems.

The power control may use the training sequence to set the power controland may be employed with any appropriate type of modulation, e.g. Edgeor GMSK modulation. This-feature, preferably as part of a system usingdigital ramping techniques, allows a simple and low cost power controlsystem to be implemented.

The Digital Power Control scheme according to the invention is differentfrom the existing Analog scheme. The power is controlled in open loopmode, i.e. no power corrections are made during the measured timeslot.The output power is set on the basis of information measured in theprevious timeslot.

The Digital Power Control method also has some advantages in that can itbe utilised when implementing a power control method for multicarriertransmitter.

The Digital Power Control method operates in an open loop basis, usingthe midamble of the burst for power measurement. Compared to the analogpower control used e.g. for 8-PSK modulated signal, the controllingcircuit is open, thus there is no realtime feedback circuit to thecontroller. The method and device according to the invention does notsuffer from the problems of the analog ones.

Monitoring the known midamble will give an exact information on theoutput power, provided that, as usual, the measuring circuit(integrator, integration time, zeroing) works properly and does notproduce any error.

As the system is open loop, in that no adjustments are performed duringthe measured burst, there is a reduction in the dynamic rangerequirements of the lineariser. As power ramping is performed in thedigital domain, over- or undershooting of the ramping waveform does notoccur. Further, the same power control system can be used with anymodulation scheme, provided that it has a known midamble.

Further, the number of parts required to implement the Tx lineup isreduced, reducing costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a first embodiment of the invention which comprises abasic control loop,

FIG. 2 shows the structures of normal bursts for EDGE and GMSK,

FIG. 3 illustrates a further embodiment of the present inventionincluding a single control loop,

FIG. 4 shows the detector dynamic range in an embodiment of the presentinvention,

FIG. 5 illustrates a further embodiment of the present inventionimplemented for a smart antenna case,

FIG. 6 shows another embodiment of the present invention illustratingthe places for power control in a smart antenna structure,

FIGS. 7, 8 show details of an embodiment of the present invention, andin particular illustrate the calibration structure,

FIG. 9 shows signals and their correlation peaks, and

FIG. 10 shows a coupled antenna array usable in the embodiments of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

The described Digital Power Calibration and/or Control scheme inaccordance with the invention is for instance applicable in a GSMtransceiver. The power calibration and/or control method and devices aredesigned and applicable for Smart Antenna applications or non SmartAntenna applications. Generally, a smart antenna system combinesmultiple antenna elements with a signal-processing capability tooptimize its radiation and/or reception pattern automatically inresponse to the signal environment.

The purpose of the power control system is to control the output powerof the transmitter in several steps, e.g. sixteen steps of 2 dB. Powercontrol is also responsible for meeting the power versus timerequirements and switching transient requirements specified in theDigital Cellular Telecommunications System (Phase 2+) for GSM (GlobalSystem for Mobile Communications).

According to a preferred implementation of the invention, the output ofthe Power Amplifier is detected during the training sequence, averagedusing an integrator, and then digitised with an ADC (Analog to DigitalConverter). This digitised signal is fed to the power control algorithmwhich can be implemented as hardware, e.g. an ASIC (Application SpecificIntegrated Circuit), or in software, e.g. residing in an embeddedprocessor. The algorithm compares the measured output to the desiredsignal level, and forms an error signal which steps the RF attenuator tothe correct level.

FIG. 1 shows an embodiment of the invention employing such a structureand functioning.

The power control device of FIG. 1 includes an attenuator 1 to which theRF signal to be applied to an antenna (not shown) is supplied. Theattenuator 1 is controllable as regards its gain, and applies itsoutput, e.g. the power-controlled RF signal, to a power amplifier (PA) 2having its output connected to a line 3 which leads to the antenna. Forpower detection, a detector circuit 4, such as a diode detector circuitis coupled to the PA output (line 3) via an appropriate coupling meanssuch as a directional coupler. The analog output signal of detectorcircuit 4 is supplied to an analog-digital converter (ADC) 5 eitherdirectly or preferably via an integrating or averaging means. The outputof the ADC 5 is applied to a baseband module 6 and represents themeasured power level.

The baseband module 6 includes an error correction device such as theshown summing means 7 which receives the output signal of ADC e.g. atits inverting input, and a reference value representing the desiredpower level, e.g at its non-inverting input. The resulting error signaloutput from summing means 7 is applied to the control input ofattenuator 1 for controlling its gain appropriately.

There are four main fundamental features (implementable either solely orin arbitrary combination) within the digital power control designaccording to the shown embodiments which are:

-   -   Baseband Ramping within the control means;    -   Open Loop Static Control (e.g. Power Levels 0 to 6);    -   Dynamic Control set within the control means (e.g. Power Levels        7 to 15);    -   Estimation of output Power is based upon the digitised Training        Sequence of the output signal.

These features are explained in more detail in the following.

The Baseband Ramping is achieved in an appropriate element such as inthe transceiver, e.g. in an ASIC chip.

The output of the modulator is digitally multiplied by a programmablesmooth ramp profile, which brings up the power gradually to avoidswitching transients. This ramped digital signal is then used as theinput to a DAC (Digital to Analog Converter)—the output of which can beup-converted and amplified to the correct level. The output signal ofthis DAC may represent the desired value “Ref.” applied to summing means7 as shown in FIG. 1.

The power ramp is generated in a DDS (Direct Digital Synthesis)structure and is synchronized to the falling edge of the Power ControlScheme clock, e.g. PWC (Pulse Width Control) clock. The power ramp goesdown between timeslots in all cases. The Power control unit gets itstiming, slope and power level information preferably from a powercontrol table e.g. within the ASIC.

As regards Open Loop Static Power Level Control, the control of thestatic power levels, Power Levels 0 to 6, may e.g. be effected by asingle attenuator, e.g. a 30 dB, 2 dB step digital Attenuator, at RF(Radio Frequency). The attenuator receives its information from theASIC. This attenuator is also used to take out unit to unit variationsin components and the effects of temperature variations. The staticpower control serves to reduce DAC dynamic range requirements.

The Dynamic Power Level Control is effected in the power control means,preferably using a basic structure as shown in FIG. 1. Preferably, adigital multiplier, before the modulator output, sets the output powerfor dynamic levels PL7 to PL15 (PL=Power Level).

As regards Training Sequence Detection, rather than trying to detect thewhole envelope of the timeslot, the invention preferably detects onlythe midamble training sequence. The training sequence is a fixed bitsequence which compensates for the effects of multipath fading andallows synchronisation. The output of the detector is then preferablyaveraged using an integrator and then converted to a digital signal ofe.g. 12 bit.

FIG. 2 shows the structure, in the time domain, of a normal burst ofdata for both EDGE and GSM. The position of the training sequence(midamble) within each burst is highlighted.

The bursts for EDGE or GMSK are standardised and include tails 8 at thebeginning and end, a midamble (training sequence) 10 in the midst of theburst signals, and information sections 9 between the training sequence10 and the tails 8. FIG. 2 indicates the bit lengths of the individualsections of the bursts, as well as the total bit lengths of the bursts.

This approach has two main advantages. Firstly the position of thetraining sequence and its duration within the burst are fixed andsecondly a diode detector circuit is able to detect the output power forall output power levels.

The embodiment preferably comprises only a single power control loop.

A simplified version of the power control algorithm is suitable forinclusion in the power control means; e.g. ASIC. As before, the powercontrol compares the required output power with the measured power, andappropriately steps the attenuator and digital multiplier within thepower control chip, e.g. ASIC.

FIG. 3 shows the main components of a single control loop.

The power control shown in FIG. 3 includes a power control means 11which is connected to a baseband module (baseband board BBB) 12 whichmay be similar to baseband module 6 of FIG. 1 and which applies, at itsoutput DL, appropriate signals to the power control means 11. The powercontrol means 11 includes a transmitter chip 13 which may be an ASIC oran embedded processor. A static power control means 14 such as acontrollable amplifier or attenuator is connected to the RF output ofchip 13. The output of static power control means 14 is connected to theinput of power amplifier 15 which outputs the signals to be transmittedto an output 16 connected to one or more antennas (not shown).

The power control means 11 comprises a directional coupler 17 forsensing the output power of power amplifier 15, an attenuator means 18,a detector means 19, an integrator 21, an ADC (Analog to DigitalConverter) 22, a power detection section 23, and an algorithm section24. The power detection section 23 comprises a static control partissuing a control signal to static power control means 14 forcontrolling the actual static power control level, as well as a powerdetection section issuing a control signal which is applied, via line20, to the control input of detector means 19.

The power detection section 23 generates the control signal on line 20with a timing so as to operate the detection section.19 only when thepower amplifier outputs the midamble (training sequence) 10 shown inFIG. 2.

Therefore, the detector means 19 is controlled using a time-window foractivating the detection,section only during training sequence, and forstopping the detection function of detector means during the other timesof the time slot signal (tails 8 and information sectors 9 as shown inFIG. 2). As the bit difference, and therefore the time difference,between start of a burst (starting with the front tail 8) and the beginof the training sequence 10 is fixed for every burst, the controlsection 23 can easily generate the control signal on line 20 byproviding a time delay between start of a burst and start of the controlsignal sufficient so as to open the detection function of detector means19 only when the first bits of the midamble are occurring at the inputof the detector means 19. Likewise, the time window for detecting the PAoutput signal is closed at or before the occurrence of the last bits ofthe midamble 10, the total time duration of the midamble being known tothe system beforehand in accordance with the standardised burst form.

In the following, the Power Detector and Integrator Circuit is describedin more detail. The Power detector and Integrator circuit essentiallyconsists of three main parts, a directional coupler 17, the analoguedetector circuit 19 and the Analog to Digital Conversion circuit 22. Thehighest possible coupling factor is used to minimise through loss andreduce the power dissipation in the attenuator 18 connected to thecoupled output arm. The coupler 17 must also drive the detector means 19with sufficient power so as to maintain adequate sensitivity at thelowest power level, i.e. Power Level 15.

The output from the coupled port of the directional coupler 17 drivesthe detector means 19, e.g. detector, diode matching circuit, via theattenuator 18 of at least 6 dB which is used to improve the detectormatch and set the required power level at the input to the detector 19.The matching circuit is tuned to achieve high sensitivity at low powerlevels over the GSM 900 band.

Following the detector diode matching circuit is the integrator 21 whichmay include a temperature compensation circuit. The purpose of theintegrator 21 is to average out the amplitude variations inherent in theEDGE signal and hence to reduce the error in the sampled powermeasurement.

The output of the integrator 21 feeds into the ADC 22 which converts thedetected analog voltage into a digital output which may be a word havingan appropriate number of bits. In the case of this single loop example,this digital word is fed directly into the power control chip 13, 23,where it is compared to a reference.

With regard to Detector Dynamic Range, the power detector circuit isimplemented to operate monotonically over at least the range of 36 dB,from 3 dB above to 33 dB below the nominal full power output.

The power detector circuit preferably provides an absolute accuracy of±0.5 dB over the power range 0 to 17 dB below nominal PA GMSK full poweroutput (PA=Power Amplifier). In addition it preferably provides anabsolute accuracy of ±1.0 dB over the power range from 17 dB to 33 dBbelow nominal full power output.

The breakdown of the 36 dB detector range requirement is representedgraphically in FIG. 4 (dynamic range 25) and is as follows:

-   -   3 dB for PA overdrive under fault conditions (no power accuracy        requirement);    -   3 dB difference in mean power level between EDGE and GMSK        modulation;    -   14 dB for the 7 static power steps (i.e. 8 power levels);    -   16 dB for the 8 dynamic power steps (i.e. 9 power levels).

In the following, details of the algorithm stored in algorithm section24 are described. The algorithm maintains a table of gain values onvarious channels. The table index will be sent by the baseband board 12to the power control means. The algorithm is told the static power level(i.e. the maximum transmit power of the basestation due to geographicalconstraints) in an initialisation message and is told the desired outputpower in each downlink burst message. The algorithm calculates thedynamic power level, i.e. the amount by which the base station isbacked-off from the static power, which is used to digitally scale themodulator output.

The gain value stored in the table is preferably provided as a ramp orstaircase with small increments, e.g. in ⅛th dB increments, in the rangefrom 0 to e.g. 31.875 dB. This gain value is used to drive a stepattenuator in the transmit chain, with a step size of either 0.5 dB, 1dB or 2 dB. The remainder when the gain table setting is divided by thestep attenuator resolutions is used to digitally scale the modulatoroutput.

The output power is measured during the training sequence 10, preferablyusing either an integrator to average the power or by taking multiplereadings, and the gain table setting is updated based on the differencebetween the wanted and measured power.

If the difference is less than some pre-determined value ådB, the valueis left unchanged. If greater than ådB but less than 2 dB, the table ismoved by one step (i.e. ⅛th dB) in the appropriate direction. If 2 dB ormore, the table is stepped by 16 (2 dB), to accelerate convergenceduring warm-up. If the power level is below some programmable cut-off,the table is only stepped by one unit if the difference is 2 dB or more,to account for the detector being less accurate at low power levels.

The mapping from channel number to table index will be done by thebaseband software. A simple but effective mapping would be to assignthree channels to each table entry, but a better mapping could bedetermined if the number and distribution of channels is known.

The static attenuation, i.e. the control of the static power levels,Power Levels 0 to 6, is effected by attenuator 14, e.g. a single 30 dB,2 dB step digital attenuator, at RF. The attenuator 14 receives itsinformation from the power control chip 13, e.g. ASIC. This attenuator14 is also used to take out unit to unit variations in components andthe effects of temperature.

FIG. 5 shows a further embodiment of the invention which includesmultiple TRX's configured in a smart antenna implementation. Here thetransmit section of the transceiver is split into three sections: TRX(s)28, the interconnect matrix 27 and Power Amplifier module(s) 26. Thedetected output power information is then detected in the same manner asin the above described example but then passed from power reportelements via line 30 to Baseband Boards 29 where it is used to adjustthe power settings.

The method by which the detected data is passed back to the basebandmodule may be application specific.

There are for example up to eight antennas in the Smart Antenna case, sothere will be up to eight power control loops. The C/I (Carrier toInterference ratio) can be improved by running the outer antennas at alower power level, which reduces the sidelobe power. The poweradjustment on the antenna array, called a beam taper, will be introducedby backing off the vector modulators in the control loops for the outerantennas. The vector modulators are also responsible for phasing theantennas and hence steering the beam.

The Smart Antenna system will require antenna calibration bursts to besent, in the GSM idle slots. It is sufficient to use just these burststo calibrate the power control loop, as long as a suitably smart powercontrol algorithm is used. The simple measure-and-correct algorithm usedin the non-smart case described above would possibly lead tounsatisfying results in some cases. Most gain variations in the transmitpaths are going to be due to temperature changes in the PAs andcouplers, so will be roughly independent of frequency. There are gaineffects that depend strongly on frequency, such as temperature changesat the SAW (Surface Acoustic Wave) filter, but these will happen over amuch longer timescale than PA temperature changes.

This leads to an algorithm which measures the error on one channel,corrects that channel, and then applies a proportion of that correctionto all channels assuming that a large proportion of that error wasfrequency-independent. The process of exactly correcting an error willrequire a division operation, which is easiest done in a microprocessoror DSP, rather than implementing, as an alternative, the algorithmdirectly in hardware.

Gain control is preferably performed as a part of gain/phasecalibration. The power control algorithm in the Smart Antenna situationis difficult to separate from the phase/gain calibration that is alsooccurring. The antenna calibration hardware will produce a set of phasesand relative gains for each antenna path through a particular TRX. Thepower-measuring circuits in the PA's for power control will produceabsolute powers for each PA output. There is a need to reconcile theabsolute and relative power measurements, especially if they conflict.The power control operations will involve stepping attenuators in thedifferent transmit chains, and this will alter the phase through thatpath, requiring another phase calibration.

Power/gain control can be done in four places in the transmit path, inthe Smart Antenna option. These places are highlighted by arrows in FIG.6.

The dynamic power is input, via line 33, to a digital multiplier 32 in apower control chip 31, e.g. ASIC. This gives fine, linear control of theoutput power of all antenna paths. Using this approach degrades thenoise floor, so it can only be used for dynamic power setting plus othersmall increments.

A common step attenuator 34 gives coarse control over all paths, andwill probably be used only for setting the static power level. Asplitter 35 distributes the output signal of attenuator 34 to severalantenna paths which each include a coarse path attenuator 36, a gain &phase adjuster 37 which may be implemented as a linear vector modulator,an attenuator 38 for feedback power control, a power amplifier 39, andan antenna 40.

A reference coupler 72 is placed before the splitter 35, preferably atthe line between the attenuator 34 and the splitter 35. This referencecoupler 72 is connected to other circuit path as shown in FIG. 8.

The coarse path attenuators 36 give a good range, e.g. 30 dB, ofattenuation, but in coarse steps of e.g. 2 dB, that will affect thephase of the signal. System must be calibrated after stepping thisattenuator 36.

The gain & phase adjusters 37 can be assumed to be fine-step powercontrolling devices, which means that the device must have beencharacterised accurately. This table should allow phase and gain to beset independently of each other.

The optional autonomous attenuators 38 driven by temperature-sensingequipment in the power amplifiers 39 will only affect phase to a smalldegree, but this may be significant.

In the following, the algorithm is described. The algorithm maintains atable of gains, in the range 0 to 30 dB with a high precision for eachTRX path and each channel setting in use. These gains are approximatelyequal to the amount of attenuation which has to be provided in thecoarse path attenuator 36 and vector modulator 37, holding the commonstep attenuator 34 at the correct setting for this static power level,so that the maximum input to the digital multiplier (4095) will providethe correct static power level at the PA output. An approximation ispreferably provided because the coarse path attenuator 36 will not haveexactly 2 dB steps.

The inputs to the algorithm are the static power level, the dynamiclevel of this burst (i.e. the amount in dBs that it is backed-off fromthe maximum allowed power for this BTS), and the tapering of theantenna.

The common attenuator 34 is preferably set to the static power level. Itis possible to account for gain drifts in the whole antenna array here,but this may be unnecessarily complicated.

The digital multiplier 32 is preferably set to 4095×10^(d/20) where d=0,−2, −4, . . . is the dynamic power level in dB. The beam taper orprofile should be added to the vector modulator settings. The tapercannot be done by changing the coarse path attenuators 36, because thetaper can change from one timeslot to another, but the phase must remainconstant for every timeslot between calibrations. The taper needs to bechangeable to allow packet services to be broadcast to many recipients,while targeting traffic channels to a single user.

In the following, the architecture, function and interfaces of acalibration module 50 representing an embodiment of the invention andusable in the above described structure will be explained with referenceto FIGS. 7 to 10.

The system supports Smart Antennas, which include an array of antennasto allow beam steering. Smart Antenna performance depends greatly on theaccuracy of the relative phases and amplitudes of the signal fed to eachantenna. The signals to each antenna customarily go through differentpaths (amplifiers, filters and cables) resulting in relative amplitudeand phase errors between the paths. If these errors are not calibratedout by the system, the Smart Antenna performance is degraded.

This description deals with the internal design and interfaces forCalibration Module (CM) 50, the system which measures the path phase andamplitude errors and reports them to the TRXs to allow them tocompensate for the errors.

The CM 50 is able to calibrate both transmit and receive paths of theBTS. The CM 50 is responsible for:

-   -   transmitter calibration involving receiving, demodulating and        processing bursts transmitted by the TRXs within the BTS;    -   receiver calibration involving injection of GSM RF signals at        the masthead which are received and processed within the TRXs of        the BTS;    -   control of the calibration process including selection of TRX        and frequency to calibrate, and timing of calibration bursts.

The CM 50 shown in FIGS. 7, 8 is basically implemented for GSM 900 butmay optionally be GSM 900 and GSM 1800 compatible, or may be designedfor another communication standard.

The CM unit (CU) 50 contains the RF and sampling electronics required tomeasure the calibration bursts received from the BTS, and to generatebursts to send to the BTS.

FIGS. 7, 8 show the internal architecture of the CM 50 integrated e.g.in a MS (Mobile Station), i.e. the CM architecture based around (e.gGSM) MS transceiver and controller. In the following, the function ofeach block is defined.

The CM 50 has no power amplifier.

A RF Switch/Attenuator Block 53 is implemented as a switch block whichconsists of three RF switches 64, 69, 70. These RF switches configurethe CM for transmit or receive, allow the sampling of signals fromeither a Summing Coupler 74 or from Reference Coupler 72, and blank offthe transmitter during power up of a transmit VCO 61.

The reference coupler 72 is used by the CM 50 to measure a referencephase and gain value to compare to the measured gain and phase valuesfrom the N columns.

The outer input/output (represented by a longer line) of summing coupler74 shown in FIG. 8 is connected to input/output 51 shown in FIG. 7.Likewise, the output of reference coupler 72 shown in FIGS. 6, 8 isconnected to input 52 shown in FIG. 7.

In detail, the switch block 53 contains:

-   -   a sample switch 69 for allowing the receiver input to sample        either the Summing Coupler or the Reference Coupler inputs. The        switch 69 is capable of rapidly switching between the two within        e.g. 4 microseconds;    -   a transmit-receive switch 70 allowing either the transmitter or        receiver to be connected to the Summing Coupler 74 port. The        transmit-receive switch 70 is capable of switching within e.g. 4        microseconds;    -   a blanking switch 64 with high (e.g. 30 dB) isolation which can        prevent transmission into the summing coupler by diverting        transmit energy into a load. This is required because the        translational loop of the GSM chip is activated in the slot        before transmission occurs and it is necessary to isolate the        transmitter while it is settling. This switch 64 is capable of        switching within e.g. 4 microseconds; and attenuators to reduce        the levels input and output from the CM to acceptable levels.        Attenuation shall be distributed between the Summing Coupler and        the BTS controller or BTS O&M.

The CM provides greater than 30 dB isolation between the Summing andReference Coupler ports in both transmit and receive mode.

The switch block 53 also contains any driver circuits necessary for theswitches if TTL drive from the BTS controller or BTS O&M is notsufficient.

A Transceiver 54, e.g. a GSM transceiver, provides the transceiverfunctions. The architecture of the transceiver 54 as well as thearchitecture of the switch block 53 (RF block architecture) are shown inFIG. 8.

The transceiver block 54 comprises an integrated mobile station chip(ASIC) with supporting RF components including attenuators, SAW filtersand VCOs.

The transceiver block 54 receives RF signals from the Reference Coupler72 and transmits or receives RF signals from the Summing Coupler 74. Ituses as a reference the BTS system master clock.

The transceiver 54 is capable of reception followed by transmission witha e.g. three slot offset as used in standard GSM Mobile Stations.

Any GSM compliant mobile station RF processor chip 60 is suitable forthe CM 50.

A baseband interface means (e.g. ASIC) 55 provides the interface betweenthe processor 60 of the Calibration Module 50 and the BTS controller orBTS O&M, e.g. signal processor 56.

Specifically, the baseband means 55:

-   -   receives a bitstream from the BTS controller or BTS O&M 56 via a        serial I/O (Input/Output) interface, performs the GMSK        modulation and digital to analogue conversion required to send a        GMSK analogue signal to the processor 60;    -   receives GMSK baseband I/Q analogue signals from the processor        60, filters and samples them to send a digital I and O signal to        the BCC through the same serial I/O interface.

The baseband interface ASIC 55 is controlled by the same serial portused for data transmission with the addition of a small number ofdigital control lines.

The signal processing unit (signal processor) 56 provides hardwareinterfaces and host functions, the signal processing functionsassociated with calibration,and device drivers for the transceiver 54,processor 60, and the switch module 53.

In addition the unit 56 interfaces to the BTS controller or BTS O&Mwhich preferably hosts the calibration control algorithm. The unit 56may also interface directly with the BTS controller or BTS O&M whichwill execute the device drivers and signal processing functions inaddition to the control algorithm.

The signal Processing unit is preferably slaved to the BTS system clockvia the BTS controller or BTS O&M. The Signal Processing unit may be theBTS controller or BTS O&M mentioned above. The software is preferablydesigned to allow separation of the signal processing and BTS controlleror BTS O&M software.

The CM Interfaces include external interfaces and internal interfaces.The external interfaces comprise RF interfaces of the summing coupler 74(e.g. where the Summing Coupler feed cable leading to the BTS shell isconnected to the summing coupler) and of the Reference Coupler 72, aswell as BTS controller or BTS O&M interfaces.

As shown in FIG. 8, the CM 50 additionally comprises a Tx RF SAW(Surface Acoustic Wave) filter 63, a 1^(st) Rx RF SAW filter 67, a2^(nd) Rx RF SAW filter having both its input and output connected toprocessor 60, an IF SAW filter having both its input and outputconnected to processor 60, an RF VCO and IF VCO connected to processor60, a Tx VCO 61, a GSM Duplex switch 70, a 900 MHz RF switch 64,attenuators 65, 66, 68, 71, 73, buffers 62, etc.

The processor 60 is controlled by a 3 wire digital interface. Thisinterface will be used to configure the processor 60 between transmitand receive modes, and set the synthesisers to relevant frequency.

The baseband block 55 uses a 6 wire bi-directional serial interface. Theinterface clock is output from the block 55 and is an integer divisor ofthe e.g. 13 MHz input master clock, with the divisor set by an internalregister. The interface can be set in transmit or receive mode.

The interface between Switch Block 53 and BCC comprises 3 control linesto command the sample switch 69, the Tx/Rx switch 70 and the blankingswitch 64.

The internal interfaces of CM 50 include an analog differential I/Ointerface between the Converter Block of baseband block 55 and theTransceiver Block. 54, as well as an RF interface between theTransceiver Block 54 and the Switch Block 53.

In the following, the function of the CM 50 will be described.

The measurement of calibration basically has two parts, TX and Rx. Bothpreferably use a simple passive coupling network in the antenna arrayand a calibration board which works at mobile frequencies, e.g. the RFfrom a mobile station as in this implementation.

FIG. 10 shows the coupling array. Four antennas 80 are shown.

The number of antennas depends of course on the actual requirements andmay be greater or smaller than four. Each antenna 80 is coupled with adirectional coupler 81 each of which directionally couples the antennasignals (received or transmitted) to an associated line 82. All fourlines 82 are connected to a 4-way 0° splitter 83 so that the signalsapplied to one antenna 80 are coupled, with zero phase shift, to allother antennas 80 as well. Equal phase lengths from couplers 81 to endof array are provided. Likewise, the array is structured so as toprovide equal phase lengths to the splitting point. The couplingdirection is illustrated by an arrow.

To calibrate the transmit side the BTS transmits GSM dummy bursts to thecalibration board. To calibrate the Receive side the calibration boardtransmits dummy bursts to the BTS. With processing, e.g. DSP processing,the relative gain and phase values can be calculated.

During normal BTS operation, calibration takes place using the idleslots which occur once per multiframe for GSM TCH/F (TCH=TrafficChannel), HSCSD and GPRS traffic channels. Half rate channels do nothave this idle slot, and so half rate traffic on a given TRX is managedto ensure some TCH/F channels are present, allowing calibration.

During BTS start-up, calibration takes place using every frame to reducecalibration time. Each TRX shall be calibrated at each frequency in useon the BTS.

Transmit calibration may use a technique of Sequential Phase Inversion,where a series of bursts transmitted by the TRX, following splittinginto the N antenna paths, are sequentially inverted by the Gain-PhaseAdjusters. These sequentially inverted signals are measured and summedat the mast-head by the Summing Coupler 74 and passed to the CM unit fordown-conversion, sampling and subsequent signal processing.

Preferably, transmit calibration uses a technique (method) which relieson sequentially turning off some, preferably 3, of all the columns,preferably 4 columns, and measuring the phase differences. As this isdone on idle channels there is no performance degradation.

For Receive calibration, a (e.g. GSM) dummy burst is generated withinthe BTS controller and passed to the converter and transceiver blocksfor modulation onto the required GSM carrier. This burst is received ineach branch of the TRX. The amplitude and phase differences between eachpath are measured by the TRX and used as the new receive calibrationoffset.

The BTS controller is responsible for overall control of the calibrationprocess including

-   -   configuring the CM 50,    -   triggering individual calibrations,    -   signal processing of transmit calibration bursts,    -   tracking calibration status of the TRXs within the BTS.

For Transmit Calibration Control in a Smart Antenna system, the BTScontroller executes the Calibration Control application which managesthe calibration process and interfaces with the CM 50 and the TRXbaseband within the BTS.

The BTS controller maintains a calibration status table containing eachTRX and frequency within the BTS. Calibration of a given (TRX,frequency) combination is scheduled according to this table with theoldest calibrations receiving highest priority. In the case of slowfrequency hopping (SFH) the Calibration Control application uses anopportunistic approach where several (TRX, frequency) calibrations maybe in progress at any one time.

The steps involved in transmit calibration are:

-   -   1. select the TRX most in need of calibration by a weighted sum        of calibrations not yet started, calibrations in progress,        calibrations completed,    -   2. calculate which frequencies in the hopping pattern may be        used at the current FN,    -   3. select the available frequency most in need of calibration on        the chosen TRX, based on factors such as age of calibration,        current interim status of the calibration,    -   4. send a calibration message to the TRX under calibration        configuring the state of the gain/phase adjusts for the wanted        timeslot. For each burst, one of the N branches will be active,        with the phase adjuster set to 0° and gain to a nominal value.        The other branches will be set to maximum attenuation,    -   5. configure the CM to receive dummy burst(s) at the required        frequency by commanding the CM synthesisers to move to the        required frequency, the T/R switch to move to its receive        position and the sample switch to move to the Summing port,    -   6. receive and store digital samples of the first e.g. 70        symbols of the dummy burst,    -   7. after e.g. 70 symbols of the burst, command the sample switch        to move from Summing to Reference ports,    -   8. receive and store digital samples of e.g. 70 further symbols,    -   9. repeat steps 6, 7 and 8 for the N idle slots required to        calibrate an N antenna system,    -   10. following the receipt of samples of the N bursts execute a        calibration algorithm, e.g. an algorithm for calculating the        relative phase and gain differences between the N paths for the        selected TRX and frequency.

As an example, following receipt of samples of the N bursts the CM 50performs decorrelation on all of the bursts. For each burst there willbe an amplitude and phase calculation for the 70 symbols of thereference port and one for the 70 symbols from the active antennacolumn. By subtracting reference amplitude and phase from summing portreference and phase an absolute amplitude and phase is generated. Onceall N columns have been processed, one of the columns (normally one ofthe end ones) is used as the origin, with its' phase and get set aszero, with the other N columns being offset from this.

-   -   11. send a_calibration_MEASURE message to the TRX under        calibration, containing the N calibration values,    -   12. monitor TRX and CM for calibration related alarms.

The calibration burst format needs to be known by both the BTS and CMreceiver. One pre-defined burst is the dummy burst, described in the GSMspecifications 05.02 as a unique sequence of bits, with tail bits andguard period bits. This burst format shall be used for the calibration.

The BTS controller or BTS O&M executes the Calibration Signal Processingalgorithms which process received GSM bursts to derive amplitude andphase corrections. This involves correlating the received samples withGMSK modulated dummy burst samples stored within the BTS controller orBTS O&M.

Furthermore, a Timing Recovery is provided. There is always a time delaybetween the transmission of the calibration signal and its reception.This delay varies with time and can cause calibration error.

FIG. 9 shows the non-delayed signal and the delayed signal and theircorrelation peaks, and illustrates the time shift between the real andmeasured correlation peaks of these signals with and without timingoffset. The vertical lines represent the sampling times. The timingoffset is shown by a double-headed arrow and in this example correspondsto two sampling intervals.

Simulations have shown that a timing offset of a quarter of a symbol forthe signal received from the summing coupler 74 is acceptable. Thefollowing timing recovery method is preferably used to stay within thisrange.

Calibration at the time of power-up of the system or transmitter TRX(Power up calibration):

-   -   First iteration: Correlate the received signal with the expected        signal (with no timing offset) to give the timing offset to 1        symbol accuracy,    -   Second iteration: The Expected Arrival Time of the signal is        modified by +/−½ symbol according to the sign of the measured        timing offset,    -   Third iteration: The Expected Arrival Time of the signal is        modified by +/−¼ symbol according to the sign of the measured        timing offset.

On-going calibration during operation: The Expected Arrival Time of thesignal is modified by +/−¼ symbol according to the sign of the measuredtiming offset. The timing offset shall be considered frequencyindependent but TRX dependent.

A Phase Reference Recovery is provided. The Phase Reference Recoveryalgorithm is used to correct for the random phase offset of successivebursts, which is a consequence of the use of “ping pong” synthesiserswithin the TRX.

The algorithm correlates dummy burst samples measured from the ReferenceCoupler with the stored reference to calculate the phase offset of theTRX synthesiser.

Preferably, a Receive Calibration is likewise provided. The calibrationprocess may be implemented in a customary manner.

For achieving the calibration control, in a Smart Antenna system, theBTS controller or BTS O&M executes a Calibration Control applicationwhich manages the calibration process and interfaces with the CM and theTRXs within the BTS.

The BCC maintains a calibration status table containing each TRX andfrequency within the BTS. Calibration of a given (TRX, frequency)combination is scheduled according to this table with the oldestcalibrations receiving highest priority. In the case of slow frequencyhopping (SFH) the Calibration Control application uses an opportunisticapproach to calibrate the most appropriate (TRX, frequency) combination.

Receive calibration executes once per frame using Slot 7 of frames whereFN mod 26=0 (FN=Frame Number). The following steps are executed:

-   -   1. select the TRX most in need of calibration by a weighted sum        of calibrations not yet started, calibrations in progress,        calibrations completed,    -   2. calculate which frequencies in the hopping pattern may be        used at the current FN,    -   3. select the available frequency most in need of calibration on        the chosen TRX, based on factors such as age of calibration,        current interim status of the calibration,    -   4. send the configuration message to the TRX under calibration,        configuring FN, ARFCN, timeslot 7 and AGC level. On receipt of        this command the TRX shall prepare to move to the appropriate        frequency and to set the Gain Phase Adjusters to null and the        AGCs to the required setting,    -   5. the BTS controller or BTS O&M shall command the CM processor        60 to the appropriate frequency and configure the CM 50 for        transmit mode. The blanking switch 64 shall isolate the transmit        VCO 61 from the CM output. The Tx/Rx switch 70 shall remain in        Rx mode,    -   6. the BTS controller or BTS O&M shall load the dummy burst bits        into the input buffer of block 55 via the serial interface. At        the start of the appropriate timeslot the BTS controller or BTS        O&M shall trigger the modulation and D/A conversion process        within the block 55 and switch the blanking switch 64 and the        Tx/Rx switch 70 to connect the processor 60 Tx with the CM        output,    -   7. each TRX shall receive the dummy burst on its N branches and        execute the Receive Calibration algorithm to derive new        calibration values.

The format of the Receive bursts is such that the receive bursts consistof standard GSM dummy bursts.

Modulation and digital to analogue conversion of the burst are generatedby the DAC within the block 55 and filtered by the on-boardreconstruction filters. As regards burst timing, the burst transmittedby the CM is time-aligned to within ±1 symbol period of a nominal zerotiming advance value, i.e. the burst transmitted by the CM is 468.75±1symbol periods delayed from the-burst received by the CM 50.

To correct for the small timing offset caused by cable delays, the CMtransmit burst timing is corrected by a Timing Recovery offset value T₀.The T₀ shall be applied in such a way that if the transmit calibrationTiming Recovery offset acts to retard the measurement of the BTStransmit burst, the CM transmit burst shall be advanced by the sameoffset.

The burst power of the output of the processor 60 transmitter isattenuated, e.g. by 10 dB, within the CM 50 resulting in acorrespondingly attenuated power at the CM output port.

The TRX executes a Calibration Signal Processing algorithm whichprocesses GSM bursts received on each antenna path to derive amplitudeand phase corrections. This involves correlating the received sampleswith a reference dummy burst stored within the TRX BBB (BaseBand Board).The TRX calculates relative phase and amplitude differences between itsN receiver paths. The calibration procedure within the receiver does notassume that the signal injected by the CM has the same amplitude orphase between consecutive calibration bursts.

The calibration of the BTS Rx is constrained by the minimum C/I (carrierto interference) which is required to achieve accurate calibration:

-   1. the maximum power of any unwanted signal which will be received    by the BTS Rx,-   2. the C/I required to achieve accurate calibration of the wanted    signal (from simulation),-   3. these give the required minimum calibration carrier power at the    BTS input. The calibration carrier needs to be switched “off”    between calibrations, the power level when it is off preferably is    in the noise floor of the BTS Rx,-   4-6. there are various constant gains and losses for the couplers    and combiners in the system,-   7. these give the wanted carrier power level at the CM transmitter    output,-   8. a blanking switch is provided to put the CM output power into the    noise floor of the BTS, taking account of the gains and losses in    the system,-   9. an attenuator is provided to reduce the CM VCO output power to    the level required,-   10. the RF chip VCO has a fixed output power.

The Tx calibration includes two parts: measurement at the summingcoupler 74 and at the reference coupler 72. Neither puts enough powerinto the CM Rx front end to cause intermodulation products. Attenuatorsare provided:

-   1. The TRX output at maximum and minimum power,-   2-5. various gains and losses from the cables and couplers in the    system,-   6. This is the maximum and minimum power present at the CM Rx input,-   7. an attenuator is provided to bring the power at the CM Rx input    down to the maximum input power which can be input to the CM Rx.

The same calculation is performed for the summing coupler 74, with adifferent combination of couplers and cables taking account of thedifferent position in the BTS of the reference coupler 72.

The CM 50 may be integrated with the BTS controller or BTS O&M, hencethe CM 50 may need to conform with BTS controller or BTS O&M dimensions.The Calibration Module may be duplicated for redundancy.

The active components of the CM 50 are preferably designed for e.g. GSMhandsets-and have very low power consumption

Although the invention has been described above with reference tospecific embodiments, the scope of the invention also covers anyalterations, additions, modifications, and omissions of the disclosedfeatures.

1. An apparatus, comprising: a calibrator configured to calibrate thetransmission or receiving power of a transmitter or receiver in a mobilecommunication network, the calibrator including a summer connected to anantenna array of the transmitted or receiver, wherein the summer isconfigured to sum transmission or reception signals, and a commoncalibrator configured to calibrate the summed signals, wherein theapparatus is configured to transmit or receive burst signals for theantenna array and the burst signals include a training sequence; a powercontrol loop configured to control the output power of the poweramplifier, the power control loop containing a detector configured todetect the output of the power amplifier, and a controller configured tocontrol the detector so as to detect the output of the power amplifieronly during a time of output of the training sequence using atime-window to activate the detector only during the training sequenceand to stop the detection function of the detector during the othertimes, wherein the apparatus is configured to control the power based onthe detected output power; and a power detection section configured toissue a control signal which is applied to a control input of thedetector, wherein the power detection section is configured to generatethe control signal with a timing so as to operate the detector only whenthe power amplifier outputs the training sequence, wherein the powerdetection section is configured to generate the control signal byproviding a time delay between start of a burst signal and start of thecontrol signal sufficient so as to open the detection function of thedetector only when the first bits of the training sequence are occurringat the input of the detector, and to close the time window for detectingthe power amplifier output signal at or before the occurrence of thelast bits of the training sequence.
 2. The apparatus according to claim1, wherein the controller is configured to issue a control signal thatis applied to a control input of the detector, and the controller isconfigured to generate the control signal with a timing so as to operatethe detector only when the power amplifier outputs the fixed trainingsequence.
 3. The apparatus according to claim 1, further comprising: atransmission branch; a reception branch; and a first switch configuredto switch the connection of the summer either to the transmission branchor to the reception branch.
 4. The apparatus according to claim 3,further comprising: a second switch configured to switch the connectionof the transmission branch either to the summer or first switch, or to areference coupler configured to supply a reference signal to thetransmission branch.
 5. The apparatus according to claim 3, furthercomprising: a further switch provided in the transmission branchconfigured to temporarily blank the transmission branch.
 6. Theapparatus_according to claim 1, wherein the apparatus is configured tomeasure, for transmit calibration, idle timeslots with only one columnactive.
 7. The apparatus according to claim 1, wherein, when, forreceive calibration, a dummy burst is generated and modulated onto acarrier, the apparatus is configured to receive the dummy burst in eachbranch of a transmitter, to measure the amplitude and phase differencesbetween each path are measured, and to use the result of suchmeasurement as a new receive calibration offset.
 8. The apparatusaccording to claim 1, further comprising a chipset of a mobile terminalwhich is used for calibration in conjunction with the calibrator.
 9. Theapparatus according to claim 1, further comprising: a passive couplingnetwork in the antenna array and a calibration board that works at radiofrequencies in conjunction with the calibrator.
 10. The apparatusaccording to claim 1, further comprising: an open loop static powercontrol configured to control the output power of the power amplifier,wherein the open loop static power control comprises a controllableattenuator arranged upstream of the input side of the power amplifier,the controllable attenuator configured to be controlled by thecontroller.
 11. The apparatus according to claim 1, wherein theapparatus is configured to set the output power based on informationmeasured in a previous timeslot and to avoid making power correctionsduring a measured timeslot.
 12. The apparatus according to claim 1,wherein the apparatus is comprised in a smart antenna structurecomprising several antennas, including a power amplifier in each antennapath, a common attenuator, and a splitter arranged between the commonattenuator and the antenna paths, each power amplifier including anembodiment of the power control loop.
 13. A method, comprising:calibrating the power of a transmitter or receiver in a mobilecommunication network comprising an antenna array; transmitting burstsignals to, or receiving by, the antenna array, wherein the burstsignals comprise a fixed training sequence, and the transmitter orreceiver comprising a power amplifier; calibrating the transmission orreceiving power of the transmitter or receiver, wherein the calibratingcomprises summing transmission or reception signals of the antennaarray, and commonly calibrating the summed signals; and controlling theoutput power of the power amplifier by a power control loop, whereincontrolling includes detecting the output of the power amplifier in acontrolled manner so as to detect the output of the power amplifier onlyduring the time of output of the training sequence using a time-windowto activate the detector only during the training sequence and to stopthe detection function of the detector during the other times, andcontrolling the power based on the detected output power; issuing acontrol signal which is applied to a control input of the detector,wherein the issuing comprises generating the control signal with atiming so as to operate the detector only when the power amplifieroutputs the training sequence, wherein the timing is configured toprovide a time delay between start of a burst signal and start of thecontrol signal sufficient so as to open the detection function of thedetector only when the first bits of the training sequence are occurringat the input of the detector, and to close the time window for detectingthe power amplifier output signal at or before the occurrence of thelast bits of the training sequence.
 14. The method according to claim13, wherein the controlling comprises issuing a control signal thatcontrols the detecting, and generating the control signal with a timingso as to detect only when the power amplifier outputs the fixed trainingsequence.
 15. The method according to claim 13, further comprising: afirst switching a connection of a summer for performing the summingeither to a transmission branch or to a reception branch.
 16. The methodaccording to claim 15, further comprising: a second switching theconnection of the transmission branch either to the summer or to a firstswitch for performing the first switching, or to a reference coupler forsupplying a reference signal to the transmission branch.
 17. The methodaccording to claim 15, further comprising: temporarily blanking thetransmission branch.
 18. The method according to claim 13, furthercomprising: measuring idle timeslots for transmit calibration with onlyone column active.
 19. The method according to claim 13, furthercomprising, for receive calibration: generating a dummy burst;modulating the dummy burst onto a carrier; receiving the dummy burst ineach branch of a transmitter; measuring the amplitude and phasedifferences between each path; and using the result of the measuring asa new receive calibration offset.
 20. The method according to claim 13,further comprising: setting the output power based on informationmeasured in a previous timeslot, and abstaining from making powercorrections during a measured timeslot.
 21. The method according toclaim 13, further comprising: performing the method in a smart antennastructure comprising several antennas, including a power amplifier ineach antenna path, a common attenuator, and a splitter arranged betweenthe common attenuator and the antenna paths, each power amplifierincluding a power control loop.
 22. An apparatus, comprising:calibration means for calibrating the transmission or receiving power ofa transmitter or receiver in a mobile communication network, thecalibration means including a summing means, connected to an antennaarray of the transmitted or receiver, for summing transmission orreception signals, and a common calibrating means for calibrating thesummed signals, wherein the apparatus is configured to transmit orreceive burst signals for the antenna array and the burst signalsinclude a training sequence; power control loop means for controllingthe output power of the power amplifier, the power control loopcontaining a detector means for detecting the output of the poweramplifier, and a control means for controlling the detector means so asto detect the output of the power amplifier only during a time of outputof the training sequence using a time-window means for activating thedetector means only during the training sequence and for stopping thedetection function of the detector means during the other times, whereinthe apparatus is configured to control the power based on the detectedoutput power; and power detection means for issuing a control signalwhich is applied to a control input of the detector means, wherein theissuing comprises generating the control signal with a timing so as tooperate the detector only when the power amplifier outputs the trainingsequence, wherein the timing is configured to provide a time delaybetween start of a burst signal and start of the control signalsufficient so as to open the detection function of the detector onlywhen the first bits of the training sequence are occurring at the inputof the detector, and to close the time window for detecting the poweramplifier output signal at or before the occurrence of the last bits ofthe training sequence.